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  • 匿名
关注:1 2013-05-23 12:21

求翻译:采用六个共阴极的数码管,其公共端与138译码器的六个输出端对应相连,译码器的输入端与FPGA芯片的特定引脚相连,由外部输入时钟控制信号和秒计数信号,计数译码过程通过在QuartusII软件设计由FPGA芯片来完成。动态数码扫描显示方式是利用了人眼的视觉暂留效应,把六个数码管按一定顺序(从左至右或从右至左)进行点亮,当点亮的频率(即扫描频率)不大时,我们看到的是数码管逐个点亮,而当点亮频率足够大,超过人眼的分辨频率,我们将看到它们全部同时稳定显示(点亮),与传统方式得到的视觉效果完全一样。是什么意思?

待解决 悬赏分:1 - 离问题结束还有
采用六个共阴极的数码管,其公共端与138译码器的六个输出端对应相连,译码器的输入端与FPGA芯片的特定引脚相连,由外部输入时钟控制信号和秒计数信号,计数译码过程通过在QuartusII软件设计由FPGA芯片来完成。动态数码扫描显示方式是利用了人眼的视觉暂留效应,把六个数码管按一定顺序(从左至右或从右至左)进行点亮,当点亮的频率(即扫描频率)不大时,我们看到的是数码管逐个点亮,而当点亮频率足够大,超过人眼的分辨频率,我们将看到它们全部同时稳定显示(点亮),与传统方式得到的视觉效果完全一样。
问题补充:

  • 匿名
2013-05-23 12:21:38
Six common cathode digital tube, six of its public side and 138 decoder output corresponding connected to the input of the decoder and fpga chip specific pins, counting from the external input clock control signal and second signal count decoding process through in quartusii software design fpga chi
  • 匿名
2013-05-23 12:23:18
With a total of 6 CC of the digital tube, the public side of the encoder 138 with 6 output port corresponding to the input translator FPGA chip with a specific pin connected to control by an external input clock signal and second signal, the counter counts in decoding process QuartusII FPGA software
  • 匿名
2013-05-23 12:24:58
Uses six common cathodes the nixietubes, its public end is connected with 138 decoder six out-port correspondences, the decoder input end and the FPGA chip specific pin is connected, by exterior input clock controlling signal and the second counting signal, the counting decoding process through comp
  • 匿名
2013-05-23 12:26:38
Digital with six altogether cathode tube, public port corresponding to the six of the 138 decoder output connected to the decoder inputs are connected to specific pins of the FPGA chip, controlled by an external input clock signal and seconds count signals, count decoding process done by QuartusII s
  • 匿名
2013-05-23 12:28:18
正在翻译,请等待...
 
 
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