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关注:1
2013-05-23 12:21
求翻译:- Familiarity with digital logic front-end (CPLD/FPGA) design, skill in these related development process and tools (Altera quartusII, Xilinx ise, Modelsim);是什么意思?![]() ![]() - Familiarity with digital logic front-end (CPLD/FPGA) design, skill in these related development process and tools (Altera quartusII, Xilinx ise, Modelsim);
问题补充: |
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