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  • 匿名
关注:1 2013-05-23 12:21

求翻译:采用5+5分段式结构,通将DAC电容阵列分成高5位和低5位的结构,以及额外添加补偿电容的方法,提高电容之间的匹配,同时也降低了电容阵列的功耗。采用线性开关,提高采样速率。同时采用一种匹配性能较好的电容阵列进行版图布局,提高整体芯片的对称性,降低寄生参数的影响。最终在输入信号频率0.9562MHz,时钟频率125MHz 情况下SNDR后结果超过60dB。提高芯片性能的转换精度的同时,降低了芯片的整体面积以及功耗。是什么意思?

待解决 悬赏分:1 - 离问题结束还有
采用5+5分段式结构,通将DAC电容阵列分成高5位和低5位的结构,以及额外添加补偿电容的方法,提高电容之间的匹配,同时也降低了电容阵列的功耗。采用线性开关,提高采样速率。同时采用一种匹配性能较好的电容阵列进行版图布局,提高整体芯片的对称性,降低寄生参数的影响。最终在输入信号频率0.9562MHz,时钟频率125MHz 情况下SNDR后结果超过60dB。提高芯片性能的转换精度的同时,降低了芯片的整体面积以及功耗。
问题补充:

  • 匿名
2013-05-23 12:21:38
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  • 匿名
2013-05-23 12:23:18
The use of sub-paragraph 5+5 structure, through the DAC capacitor array is divided into 5-bit and 5-bit low in the structure of the additional compensation capacitance methods to improve the match between capacitance and also reduce capacitance array power consumption. A linear increase switch, samp
  • 匿名
2013-05-23 12:24:58
Uses 5+5 sectional structures, passes divides into the DAC electric capacity array high 5 and the low 5 structures, as well as the extra increase compensation electric capacity method, enhances between the electric capacity the match, simultaneously also reduced the electric capacity array power los
  • 匿名
2013-05-23 12:26:38
Using 5+5 segmented structure, pass the DAC capacitor array into high 5 and the structure of the lower 5 bits, as well as additional compensation method of capacitance, improve the match between the capacitor, capacitor array power consumption is also reduced. Linear switch is used, increase the sam
  • 匿名
2013-05-23 12:28:18
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